The present invention relates to a semiconductor device having a pump circuit and, more specifically, to a semiconductor device including a booster circuit for boosting a power supply voltage up to a predetermined one or a negative voltage generating circuit for stepping it down to a predetermined one.
A nonvolatile semiconductor memory device of an EEPROM requires a voltage which is higher than a power supply voltage when data is written to or erased from a memory cell. Such a semiconductor device includes a booster circuit for boosting up a power supply voltage to generate a high voltage. In a case where the device requires a negative voltage, a power supply voltage is stepped down to generate a given negative voltage.
FIG. 22 illustrates an arrangement of a prior art booster circuit disclosed in J. F. Dickson, IEEE Journal of Solid State Circuits, Vol. SC-11, pp. 374-8, June 1976, and FIG. 23 shows an operating waveform of the circuit of FIG. 22. In this booster circuit, N-channel MOS transistors (referred to as NMOS transistors hereinafter) 17b, 17c and 17d are diode-connected in series between a terminal 17a to which a power supply voltage Vcc is applied and an output node OUT. An oscillator 17e is constituted of a NAND circuit and a plurality of inverter circuits, and an inverter circuit 17f and a capacitor 17g are connected in series between an output terminal of the oscillator 17e and a connection node N1 of the NMOS transistors 17b and 17c. Furthermore, inverter circuits 17h and 17i and a capacitor 17j are connected in series between the output terminal of the oscillator 17e and a connection node N2 of the NMOS transistors 17c and 17d. 
In the above circuit arrangement, the oscillator 17e starts to oscillate when the level of a signal PMP supplied to one end of the NAND circuit of the oscillator 17e becomes high. The output signal of the oscillator 17e is supplied to both the connection node N1 through a series circuit of the inverter circuit 17f and capacitor 17g and the connection node N2 through a series circuit of the inverter circuits 17h and 17i and capacitor 17j. Thus, the connection nodes N1 and N2 sequentially increase in voltage and so does the output node OUT. As shown in FIG. 23, the output voltage becomes constant at voltage Vpp which strikes a balance between a current output from the booster circuit and a current consumed by a circuit (not shown) to which the output voltage is applied. To improve a voltage gain of the booster circuit, the threshold voltages of the NMOS transistors 17b, 17c and 17d are set low. Even though the threshold voltages become negative, the voltage gain can be improved if the period of a clock is sufficiently short. The NMOS transistors are therefore set at a threshold voltage of almost 0V.
The foregoing booster circuit temporarily stops operating when the signal PMP is at a low level. The potentials of the connection nodes N1 and N2 are then raised up to Vpp by a backflow of current from the output node OUT. If, then, the level of the signal PMP becomes high again to activate the booster circuit, the booster circuit operates out of a steady state for a while. The efficiency of the booster circuit or the ratio of output current to input current is considerably lowered, with the result that the booster circuit will be decreased in its operating stability. This problem depends upon the voltage amplitude of the capacitors and becomes more serious as the power supply voltage Vcc lowers. The prior art booster circuit is thus difficult to operate at a low voltage.
FIG. 24 illustrates another prior art booster circuit disclosed in J. C. Chen et al. 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 172-3, June 1996. The booster circuit comprises a P-channel MOS transistor (referred to as a PMOS transistor) 19b connected between a power supply terminal 19a to which a power supply voltage Vcc is applied and an output node OUT, a capacitor 19c one end of which is connected to the output node OUT, series-connected inverter circuits 19d and 19e for supplying a capacitor driving signal PMP to the other end of the capacitor 19c, and NMOS transistors 19f and 19g, PMOS transistors 19h and 19i and an inverter circuit 19j for controlling the PMOS transistor 19b in response to a signal ACT. The sources of the NMOS transistors 19f and 19g are grounded. The capacitor driving signal PMP is generated in response to the signal ACT.
FIG. 25 shows an operation of the booster circuit illustrated in FIG. 24. When the signal ACT is at a low level, the booster circuit is in a nonoperating state and the power supply voltage Vcc is output from the output node OUT via the PMOS transistor. If the signal ACT is set at a high level when the booster circuit starts to operate, the signal PMP at the power supply voltage Vcc is set at a high level in response to the signal ACT. Since the PMOS transistor 19b is then turned off, the output voltage is raised up to a voltage Vpp which depends upon a ratio of the capacity of a load (not shown) connected to the output node OUT. and that of the capacitor 19c. 
In the booster circuit for boosting an output voltage in the ratio of the capacity of the load to that of the capacitor, the output voltage depends upon the power supply voltage Vcc and the charging voltage of the capacitor 19c. For this reason, when the power supply voltage Vcc decreases, the output node OUT is difficult to increase up to the voltage Vpp only by the single capacitor 19c. 
As described above, in the prior art booster circuit of FIG. 22 which is repeatedly activated and inactivated, the potentials of connection nodes N1 and N2 are increased by a backflow of current from the output terminal in the transition from the inactive state to the active state. For this reason, the prior art booster circuit has a problem of decreasing in efficiency especially when a power supply voltage is low.
In the booster circuit of FIG. 24 for boosting an output voltage in the ratio of the capacity of the load to that of the capacitor, a necessary booster voltage cannot be generated when a power supply voltage is low.
The same problems as above are true of a prior art negative voltage generating circuit.
The present invention has been developed in order to resolve the foregoing problems and its object is to provide a semiconductor device having a pump circuit capable of generating a given output voltage even when a power supply voltage is decreased.
To attain the above object, a pump circuit according to a first aspect of the present invention comprises: a plurality of switching elements connected in series between a first node to which a first voltage is applied and an output node from which a second voltage other than the first voltage is output; at least one capacitor having a first terminal and a second terminal, the first terminal of the capacitor being connected to at least one connection node of the plurality of switching elements; a signal generator connected to the second terminal of the capacitor, for generating a driving signal when a control signal is first logic and stopping generation of the driving signal when the control signal is second logic; and a reset circuit connected to the connection node, for resetting a voltage of the connection node to a third voltage other than the second voltage when the control signal changes from the second logic to the first logic.
According to a second aspect of the present invention, there is provided a pump circuit comprising: a first capacitor having a first terminal and a second terminal, the first terminal being connected to an output node; a second capacitor having a third terminal and a fourth terminal, the third terminal being supplied with a first signal in an active mode; a first reset circuit connected to the second terminal of the first capacitor, for resetting the second terminal of the first capacitor to a first voltage in a standby mode; a second reset circuit connected to the fourth terminal of the second capacitor, for resetting the fourth terminal of the second capacitor to a second voltage other than the first voltage in the standby mode; and a switching element connected to the second terminal of the first capacitor and the fourth terminal of the second capacitor, for causing the first and second capacitors to be disconnected from each other in the standby mode and causing the first and second capacitors to be connected to each other in the active mode.
According to a third aspect of the present invention, there is provided a pump circuit comprising: a first booster circuit operated in response to an input signal of both first logic and second logic, the first booster circuit boosting a first voltage to generate a first boost voltage and output the first boost voltage from an output node; a second booster circuit whose output node is connected to the output node of the first booster circuit, the second booster circuit boosting the first voltage to generate a second boost voltage and output the second boost voltage from the output node when the input signal is first logic, and the second booster circuit stopping a boost operation when the input signal is second logic; and a reset circuit connected to at least one internal node of the second booster circuit, the internal node being supplied with the first boost voltage from the first booster circuit when the second booster circuit stops the boost operation, and the reset circuit resetting the internal node to a voltage which is lower than the first boost voltage when the input signal changes from the second logic to the first logic.
According to a fourth aspect of the present invention, there is provided a pump circuit comprising: a first capacitor having a first terminal and a second terminal, the first terminal of the first capacitor being connected to an output node; a second capacitor having a third terminal and a fourth terminal, the third terminal of the second capacitor being supplied with a first signal; a third capacitor having a fifth terminal and a sixth terminal and connected between the first and second capacitors; a first switching circuit connected between the output node and a terminal to which a first voltage is applied, the first switching circuit applying the first voltage to the output node when a second signal is first logic; a first reset circuit having a first node and a second node, for resetting a potential of each of the first and second nodes, the first node being connected to the second terminal of the first capacitor, and the second node being connected to the fifth terminal of the third capacitor; and a second reset circuit having a third node and a fourth node, for resetting a potential of each of the third and fourth nodes, the third node being connected to the sixth terminal of the third capacitor, and the fourth node being connected to the fourth terminal of the second capacitor, the first reset circuit including: a second switching circuit connected between the first and second nodes, for short-circuiting the first and second nodes when a third signal is second logic; a third switching circuit connected between the first node and a terminal to which a second voltage other than the first voltage is applied, the third switching circuit resetting a potential of the first node to the second voltage when a fourth signal is the first logic; and a fourth switching circuit connected between the second node and the terminal to which the first voltage is applied, the fourth switching circuit resetting a potential of the second node to the first voltage when the second signal is the first logic, and the second reset circuit including: a fifth switching circuit connected between the third and fourth nodes, for short-circuiting the third and fourth nodes when the third signal is the second logic; a sixth switching circuit connected between the third node and the terminal to which the second voltage is applied, the sixth switching circuit resetting a potential of the third node to the second voltage when the fourth signal is the first logic; and a seventh switching circuit connected between the fourth node and the terminal to which the first voltage is applied, the seventh switching circuit resetting a potential of the fourth node to the first voltage when the second signal is the first logic.
According to the pump circuit of the present invention, an input voltage is boosted up to generate a booster voltage and then output it from an output node when an input signal is first logic, and the boost operation is stopped when the input signal is second logic. A reset circuit resets at least one internal node to a voltage which is lower than the output voltage when the input signal changes from the second logic to the first logic. Since the internal node is reset to the lower voltage at the beginning of the operation, the pump circuit can start operating in a state close to the steady state. The pump circuit can thus be prevented from decreasing in boost efficiency when it starts to operate and thus the boost efficiency can be kept almost constant.
Since, moreover, a plurality of capacitors are connected in series in an active mode, a desired booster voltage can be generated easily even when a power supply voltage is lowered.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.